This invention relates to a delay circuit for a sinusoidal clock input which is continuously variable in order to provide a clock signal which is shifted in phase relative to the clock input.
Many test instruments such as oscilloscopes derive all timing information from a master clock. An example of an extremely stable master clock, which is frequently used for such applications, is a surface acoustic wave (SAW) oscillator. Such oscillators are capable of generating a sine wave at a high frequency. Five hundred MHz is a typical frequency for applications of this type.
It may happen, however, that the test instrument may encounter an input having a frequency on the order of 500 MHz, or some frequency that is the same as the output of the SAW oscillator. In such cases, where the input is to be sampled and held, the input can become synchronized to the clock pulses generated from the SAW oscillator. It would, therefore, be advantageous to be able to dither the system clock slightly so that it could not become locked to, or be in synchronization with, the data input pulses.
Also, it may be desirable in some cases to increase the sampling rate of sample and hold circuits which receive data so as to be higher than the system clock rate. It is difficult, however, to advance or retard the phase of the system clock in a precise enough manner so as to exactly double (or quadruple) the sampling rate. Also, it is sometimes necessary in dual channel digitizers that two clocks be synchronized so that sampling may take place on the two channels simultaneously. This can be difficult if data arrives at each channel's digitizer at a different time because of unequal cable length or other factors causing unequal propagation delays. It would be advantageous in such a case if one channel's clock could be phase advanced or retarded so that sampling could occur simultaneously.
In the past it has been possible to generate delayed clock pulses from a sinusoidal input by using a comparator amplifier having an RC integrator network as an input. The RC network included a variable resistor which altered the slope of the input wave, and hence, the point at which the comparator switched from a high state to a low state. The effect of this circuit is that as the slope flattens out, the phase of the output pulses become retarded in time with respect to the input because the comparator is triggered at a later time during each cycle. However, in such circuits, the input waveform frequently includes jitter and high-frequency noise. This causes uncertainty as to the time that the rising and falling input waves encounter the threshold. The result is a nonuniform and/or noisy output.
It would thus be desirable to be able to delay a system clock to provide clock pulses of varying phase relationships with respect to the phase of the system clock without introducing noise or jitter where the phase adjustment could be continuously variable over the period of the clock pulses.